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Austin Semiconductor, Inc. AS28F128J3M Q-Flash
Plastic Encapsulated Microcircuit
128Mb, x8 and x16 Q-FLASH Memory
Even Sectored, Single Bit per Cell Architecture Features
* * * * * * * * * * * * * * * * * 100% Pin and Function compatible to Intel's MLC Family NOR Cell Architecture 2.7V to 3.6V VCC 2.7V to 3.6V or 5V VPEN (Programming Voltage) Asynchronous Page Mode Reads Manufacturer's ID Code: ! MT28F128J3MRG Micron 0x2Ch Industry Standard Pin-Out Fully compatible TTL Input and Outputs Common Flash Interface [CFI] Scalable Command Set Automatic WRITE and ERASE Algorithms 5.6us per Byte effective programming time 128 bit protection register ! 64-bit unique device identifier ! 64-bit user programmable OTP cells Enhanced data protection feature with use of VPEN=VSS Security OTP block feature 100,000 ERASE cycles per BLOCK Automatic Suspend Options: ! Block ERASE SUSPEND-to-READ ! Block ERASE SUSPEND-to-PROGRAM ! PROGRAM SUSPEND-to-READ Available Operating Ranges: [-ET] -40oC to +105oC ! Enhanced ! Mil-Temperature [-XT] -55oC to +125oC
A
A1
PIN ASSIGNMENT
1 2 3 4 5 6 7 8
A6
A8
VPEN
A13
VCC
A18
A22
B
A2 VSS A9 CE0 A14 A25 A19 CE1
C
A3 A7 A10 A12 A15 DNU A20 A21
D
A4 A5 A11 RP\ DNU DNU A16 A17
E
DQ8 DQ1 DQ9 DQ3 DQ4 DNU DQ15 STS
F
BYTE\ DQ0 DQ10 DQ11 DQ12 DNU DNU OE\
G
A23 A0 DQ2 VCCQ DQ5 DQ6 DQ14 WE\
H
CE2 DNU VCC VSS DQ13 VSS DQ7 A24
64-Ball FBGA
A22 CE1 A21 A20 A19 A18 A17 A16 VCC A15 A14 A13 A12 CE0 VPEN RP\ A11 A10 A9 A8 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
NC WE\ OE\ STS DQ15 DQ7 DQ14 DQ6 VSS DQ13 DQ5 DQ12 DQ4 VCCQ VSS DQ11 DQ3 DQ10 DQ2 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE\ A23 CE2
*
For in-depth functional product detail and Timing Diagrams, please reference Micron's full product Datasheet: MT28F640J3 Rev. L Dated 04/16/04
A7 A6 A5 A4 A3 A2 A1
General Description
ASI's, AS28F128J3M Enhanced or Mil-Temp variant of Micron's Q-Flash family of devices, is a nonvolatile, electrically blockerasable (FLASH), programmable memory device manufactured using Micron's 0.15um process technology. This device containing 134,217,728 bits organized as either 16,777,218 (x8) or 8,388,608 bytes (x16). The device is uniformly sectored with one hundred and twenty eight 128KB ERASE blocks. This device features in-system block locking. They also have a Common FLASH Interface [CFI] that permits software algorithms to be used for entire families of devices. The software is deviceindependent, JEDEC ID-independent with forward and backward compatibility.
AS28F128J3MRG Revision 5.0 11/23/04
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification For Additional Products and Information visit out Web site at www.austinsemiconductor.com
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Functional Block Diagram:
Input Buffer I/O CNTL Logic ADDR Buffer/ Latch 128KB Memory Block (0) 128KB Memory Block (1) 128KB Memory Block (2) 128KB Memory Block (3) X Decode ADDR. Counter Block Erase Control WRITE Buffer
AS28F128J3M Q-Flash
Power (Current) Control
Bus Configuration Register [BCR]
CEx OE\ WE\ RP\ WP\ CLK STS VPEN WAIT VPP Switch Pump Sense Amplifiers WRITE/ERASE Bit Compare and Verify Command Execution Logic [CEL] 128KB Memory Block (n) DQ0-8 or DQ0-15 Y Dec. Y - Select Control
ISM
Status Register
Identification Register
Query
Output Buffer
Additionally, the Scaleable Command Set [SCS] allows a single, simple software driver in all host systems to work with all SCS compliant FLASH memory devices. The SCS provides the fastest system/device data transfer rates and minimizes the device and system-level implementation costs. To optimize the processor-memory interface, the device accommodates VPEN, which is switchable during BLOCK ERASE, PROGRAM, or LOCK BIT configurations and in addition can be hard-wired to VCC all dependent on the end application(s). VPEN is treated as an input pin to enable ERASING, PROGRAMMING, and BLOCK LOCKING. When VPEN is lower than the VCC lockout voltage (VLKO), all program functions are disabled. BLOCK ERASE SUSPEND mode enables the user to stop BLOCK ERASE to READ data from or PROGRAM data to any other blocks. Similarly, PROGRAM SUSPEND mode enables the user to SUSPEND PROGRAMMING to READ data or execute code from any unsuspended block(s).
AS28F128J3MRG Revision 5.0 11/23/04
VPEN serves as an input with 2.7V, 3.3V or 5V levels for application programming. VPEN in this Q-Flash device can provide data protection when connected to ground. This pin also enables PROGRAM or ERASE LOCKOUT functions/controls during power transitions. This device is an even-sectored device architecture offering individual BLOCK LOCKING that can LOCK and UN-LOCK a block using the SECTOR LOCK BITS command sequence. Status [STS] is a logic signal output that gives an additional indicator of the internal state machine [ISM] activity by providing a hardware signal of both the status and status masking. This status indicator minimizes central processing unit overhead and system power consumption. In the default mode, STS acts as an RY/BY\ pin. When LOW, STS indicates that the ISM is performing a BLOCK ERASE, PROGRAM, or LOCK BIT configuration. When HIGH, STS indicates that the ISM is ready for a new command.
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification For Additional Products and Information visit out Web site at www.austinsemiconductor.com
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Three Chip Enable (CEx) pins are used for enabling and disabling the device by activating the device's control logic, input buffer, decoders, and sense amplifiers. BYTE\ enables the device to be used in x8 or x16 configuration. Byte=Low (logic 0) selects and 8-bit mode with address zero (A0) selecting the High or Low Byte and Byte=High (logic 1) selects the 16-bit or Word mode. When the device is in Word mode, address one (A1) becomes the low order address bit and address zero (A0) becomes a no-connect (NC). RP\ is used to reset the device. When the device is disabled and RP\ is at VCC, the STANDBY mode is enabled. A reset time (tRWH) is required after RP\ switches to a High (logic 1) and the outputs become valid. Likewise, the device has a wake time (tRS) from RP\ High until WRITES to the Command User Interface [CUI] are recognized, RESETS the ISM and clears the status register.
Capacitance
Parameter/Condition Input Capacitance Output Capacitance Symbol Cin Cbyte Cout Typ 5 14 5 Max 8 16 12 Units pF pF pF
AS28F128J3M Q-Flash
Chip Enable Truth Table
CE2 VIL VIL VIL VIL VIH VIH VIH VIH CE1 VIL VIL VIH VIH VIL VIL VIH VIH CE0 VIL VIH VIL VIH VIL VIH VIL VIH Device Enabled Disabled Disabled Disabled Enabled Enabled Enabled Disabled
Absolute Maximum Ratings
Voltage Temperature under Bias Storage Temperature For VCCQ=2.7v to 3.6v Voltage on any pin Short Circuit Current Min -55 -65 -2 Max 125 125 5 100 Units
0
Notes
C
0
C V 1
mA
Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum conditions for any duration or segment of time may affect device reliability.
Pin Description Table:
Signal Name Address Symbol Type A0, A1, A2. A3, Input A4, A5, A6, A7 A8, A9, A10, A11 A12,A13,A14,A15 A16,A17,A18,A19 A20,A21,A22,A23 CE0, CE1, CE2 Input Input WE\ Input RP\ OE\ BYTE\ VPEN Input Input Input Pin 32,28,27,26, 25,24,23,22, 20,19,18,17, 13,12,11,10, 8,7,6,5, 4,3,1,30 14,2,29 55 16 54 31 15
Notes 1: All specified voltages are with respect to GND. Minimum DC voltage is -0.5v on input/output pins and -0.2v on Vcc and VPEN pins. During transitions, this level may undershoot to -2.0v for periods Description Address Inputs during READ and WRITE Operations. A0 is only used in x8 mode and will be a NC in x16 mode.
Chip Enables Write Enable Reset/Power-Down Output Enable Byte Mode Control Programming Voltage
Status Pin/Flag
STS
Output
53
Input/Output Voltage Supply Voltage Digital Ground No Connect(s)
VCCQ VCC GND NC
Supply Supply Supply -
43 9, 37 21, 42, 48 1, 30, 56
Three Chip Enable pins for Multiple devices. See chart for function Write Control Reset/Power-Down, When Low the control pin resets the status Reg. and ISM to array READ mode. Ouput Enable control enable data output buffers when Low, and when High the output buffers are disabled Configuration Control pin. When High the device is in x16 mode, when Low the device is in Byte mode (x8) Necessary Voltage pin for Programming, Erasing or configuring lock bits. Typically connected to VCC. When VPENAS28F128J3MRG Revision 5.0 11/23/04
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification For Additional Products and Information visit out Web site at www.austinsemiconductor.com
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Bus Operations:
MODE Read Array Output Disable Standby Reset/Power-Down Read Identifier Codes Read Query Read Status (ISM off) Read Status (ISN on) Write Notes 1 2 3 4 5 6 7 Refer to DC Characteristics. When VPENAS28F128J3M Q-Flash
4 5 Dout Din
3,6,7
DC Electrical Characteristics:
(VDD=3.0v-5%/+10%,TA=Min/Max temperatures of Operational Range chosen)
Symbol Vcc VccQ ILI ILO VIL VIH VOL VOH VPENLK VPENH VLKO ICC1 ICC2 ICC3 Parameter Supply Voltage Isolated Input/Output Supply Input Load Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Program Voltage Lockout Program Voltage Vcc Lockout Voltage Standby Current Power-Down Current Page Mode READ Current Asynchronous READ Mode Current PROGRAM or set LOCK BITS Current BLOCL ERASE or CLEAR BLOCK LOCK bits Current PROGRAM SUSPEND or BLOCK ERASE SUSPEND Current Test Conditions Min 2.7 2.7 Max 3.6 3.6 +/- 1.0 +/-10.0 0.8 VCCQ+0.5 0.4 0.2 Units V V uA uA V V V V V V V V V uA uA uA mA mA mA mA mA mA Notes
Vin=VccQ or GND, VCC=VCC Max., VCCQ = VCCQ Max Vin=VccQ or GND, VCC=VCC Max., VCCQ = VCCQ Max
-0.5 2
VccQ=VccQ (MIN), IOL = 2mA VccQ=VccQ (MIN), IOL = 100uA VccQ=VccQ (MIN), IOH = 2.5mA VccQ=VccQ (MIN), IOH = 100uA
1 1 1,2 1 3,4,5 4,5,6 1
0.85xVCCQ VCCQ-0.2 0.8 3.6
CMOS Inputs; VCC= VCC (MAX), Device Enabled, RP\=VCCQ+/-0.2v TTL Inputs; VCC=VCC (MAX): Device Enabled, RP\=VIH RP\=GND,+/-0.2V; IOUT (STS)=0mA CMOS Inputs; VCC=VCC(MAX); VCCQ=VCCQ(MAX) using standard 4-word page mode READS; Device is enabled; f=5MHz; IOUT=0mA CMOS Inputs; Vcc=Vcc(MAX); VCCQ=VCCQ(MAX) using standard 4-word page mode READS; Device is enabled; Ff=33MHz; IOUT=0mA CMOS Inputs; VCC=VCC(MAX); VCCQ=VCCQ(MAX) using standard work/byte single READS; Device Enabled; f=5MHz; IOUT=0mA CMOS Inputs, VPEN=VCC TTL Inputs, VPEN=VCC CMOS Inputs, VPEN=VCC TTL Inputs, VPEN=VCC Device is Disabled
2.2 50 90 50 3 8 9 17 17 17 17
220 2000 120 10 15 50 60 70 70 80 10
ICC4 ICC5 ICC6 ICC7
Notes [1] [2] [3] [4] [5] [6] Sampled, not 100% tested Includes STS ICCWS and ICCES are specified with the device deselected. If the device is read or written while in ERASE SUSPEND mode, the device's curent draw is ICCR or ICCW BLOCK ERASE, PROGRAMMING, and LOCK BIT configurations are inhibited when VPENAS28F128J3MRG Revision 5.0 11/23/04
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification For Additional Products and Information visit out Web site at www.austinsemiconductor.com
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Austin Semiconductor, Inc. AS28F128J3M Q-Flash
Memory Command Set Operations:
Command READ ARRAY READ IDENTIFIER CODES READ QUERY READ STATUS REGISTER CLEAR STATUS REGISTER WRITE TO BUFFER WORD/BYTE PROGRAM BLOCK ERASE BLOCK ERASE/PROGRAM SUSPEND BLOCK ERASE/PROGRAM RESUME CONFIGURATION SET BLOCK LOCK BITS CLEAR BLOCK LOCK BITS PROTECTION PROGRAM Key: [IA] [ID] [BA] [QA] [PA] [QD] [SRD] Notes [1] [2] [3] [4] Scalable or Basic Command Set [SCS or BCS] SCS / BCS SCS / BCS SCS SCS / BCS SCS / BCS SCS / BCS SCS / BCS SCS / BCS SCS / BCS SCS / BCS SCS SCS SCS First Bus Cycle Bus Cycles Operation Address 1 WRITE X >/= 2 WRITE X 2 1 >2 2 2 1 1 2 2 2 2 WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE X X X BA X BA X X X X X X Data FFh 90h 98h 70h 50h E8h 40h or 10h 20h B0h D0h B8h 60h 60h C0h WRITE WRITE WRITE WRITE X BA X PA CC 01h D0h PD Second Bus Cycle Operation Address Data READ READ READ WRITE WRITE WRITE IA QA X BA PA BA ID QD SRD N PD D0h Notes 1 2 3, 4, 5 6, 7 5, 6 7, 8 7
Identifier Code address Data read from identifier Code Address within a Block Query data base Address Address of Memory location to be programmed Data read from Query data base Data read from Status Register
[5] [6] [7] [8]
Following the READ IDENTIFIER CODES command, READ operations access manufacturer, device, and block lock codes. If the ISM is running, only DQ7 is valid; DQ15-DQ8 and DQ6-DQ0 are placed in High-Z After the WRITE-to-BUFFER command is issued, check the XSR to make sure a buffer is available for WRITING The number of Bytes/words to be written to the write buffer = n+1, where n=byte/word count argument. Count ranges on this device for byte mode are n=00H to n=1Fh and for word mode, n=0000h to 000Fh. The third and consecutive bus cycles, as determined by n, are for writing data into the write buffer. The CONFIRM command (D0h) is expected after exactly n+1 WRITE cycles; any other command at that point in the sequence aborts the WRITE-to-BUFFER operation. The WRITE-to-BUFFER or ERASE operation does not begin until a CONFIRM command (D0h) is issued Attempts to issue a BLOCK ERASE or PROGRAM to a locked block will fail Etiher 40h or 10h is recognized by the ISM as the byte/word program setup PROGRAM SUSPEND can be issued after either the WRITE-to-BUFFER or WORD/BYTE PROGRAM operation is inititated. The CLEAR BLOCK LOCK BITS operation simultaneously clears all block lock bits.
AS28F128J3MRG Revision 5.0 11/23/04
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification For Additional Products and Information visit out Web site at www.austinsemiconductor.com
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Austin Semiconductor, Inc. AS28F128J3M Q-Flash
AC Switching Characteristics:
(VDD=3.0V -5%/+10%, TA= Min. / Max. temperatures of Operational Range chosen)
Symbol Parameter Write Operations RP\ High Recovery to WE\ (CEx) going Low CEx (WE\) Low to WE\ (CEx) going High Write Pulse Width Data Setup to WE\ going High Address Setup to WE\ going High CEx Hold from WE\ High Data Hold from WE\ High Address Hold from WE\ High Write Pulse Width High VPEN Setup to WE\ going High Write Recovery before READ WE\ High to STA going Low VPEN Hold from valid SRD, STS going High WE\ High to Status Registry Busy Block Erase, Program and Lock Bit Performance Write Buffer Byte Program time (Program time 32 Bytes/ 16 Words) Byte/Word Program time Block Program time Block Erase time Set Lock Bits time Clear Block Lock Bits time Program Suspend Latency time to Read Erase Suspend Latency time to Read Read Only Operations Read Cycle time Address to Output Delay CEx to Output Delay OE\ to Non-Array Output Delay OE\ to Array Output Delay RP\ High to Output Delay CEx to Output in Low-Z OE\ to Output in Low-Z Cex High to Output in High-Z OE\ High to Output in High-Z Output Hold from Address, Cex, or OE\ change, whichever occurs first CEx Low to BYTE\ High or Low BYTE\ to Output Delay BYTE\ to Output in High-Z CEx High to CEx Low Page Address Access Reset Specifications RP\ Pulse Low time RP\ High to RESET during BLOCK ERASE, PROGRAM, or Lock Bit configuration tRS tCS tWP tDS tAS tCH tDH tAH tWPH tVPS tWR tSTS tVPH tWB Min 1.0 0 70.0 50.0 55.0 0 0 0 30 0 35 0 200 Typ 180 11.20 0.70 0.75 10.00 0.50 25 25 Min 115 Max 654 630 1.70 5 75 0.70 30 35 Max 115 115 50 25 210 0 0 35 15 0 10 1,000 1,000 0.0 25 Min 35 Max 100 us ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Max us ns ns ns us ns 1 128Mb Units Notes
200
ns ns ns ns ns ns ns us us sec sec us sec us us
1
1 1
tWED1 tWED2 tWED3 tWED4 tWED5 tWED6 tLPS tLES
tRC tAA tACE tAOE tAOA tRWH tOEC tOEO tODC tODO tOH tCB tABY tODB tCWH tAPA
1 1 1 1 1 1 1 1 1
tPLPH tPHRH
Notes to Switching Specifications: 1. Sampled, not 100% tested
AS28F128J3MRG Revision 5.0 11/23/04
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification For Additional Products and Information visit out Web site at www.austinsemiconductor.com
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Austin Semiconductor, Inc. AS28F128J3M Q-Flash
Mechanical Diagram
TSOP, Type I, 56 Pin
(Dimensions in mm)
20.00 +/- 0.25 18.40 +/- 0.08
0.50 TYP. 14.00 +/- 0.08
0.20 +/- 0.05 0.25
0.15 +0.03, -0.02
0.10
1.20 MAX. SEE DETAIL A 0.25 Gage Plane
DETAIL A
0.10 + 0.10, -0.05
0.50 +/- 0.10 0.80 TYP.
AS28F128J3MRG Revision 5.0 11/23/04
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification For Additional Products and Information visit out Web site at www.austinsemiconductor.com
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Austin Semiconductor, Inc. AS28F128J3M Q-Flash
Mechanical Diagram
PBGA, 10mm x 13mm, 64 Ball w/1.00mm Pitch
(Dimensions in mm)
0.85 +/-0.075
0.10 C Seating Plane
C 7.00
(Bottom View)
Ball A1 Ball A1 ID 1.00 Typ.
Alt. Ball A1 ID Ball A1 Corner ID
AS28F128J3MPBG-15
OEU86
LOT CODE DATE CODE
7.00 3.50 +/-0.05
13.00 +/-0.10
XT
6.50 +/-0.05
10.00 +/-0.10 x64 @ 0.45 diameter, post reflow
1.20 Max. Solder Ball Material: 62% Sn., 36% Pb., 2% Ag.
ASI Ordering Information
Speed (ns)
0
Pkg. Comments
TSOP1-56 FBGA-64 Consult Factory, MOQ's Apply
ASI Part Number
AS28F128J3MRG-15/ET AS28F128J3MPBG-15/ET
Configuration
0
Enhanced Operating Range (-40 C to +105 C)
128Mb, x8/x16 Q-Flash 128Mb, x8/x16 Q-Flash 115 115
Extended Operating Range (-550C to +1250C)
AS28F128J3MRG-15/XT AS28F128J3MPBG-15/XT 128Mb, x8/x16 Q-Flash 128Mb, x8/x16 Q-Flash 115 115 TSOP1-56 FBGA-64 Consult Factory, MOQ's Apply
AS28F128J3MRG Revision 5.0 11/23/04
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification For Additional Products and Information visit out Web site at www.austinsemiconductor.com
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